Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-64
ID021414 Non-Confidential
See the register summary in Table 13-3 on page 13-10.
The TRCDEVAFF1 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFAC
.
13.8.58 Software Lock Access Register
The TRCLAR characteristics are:
Purpose Controls access to registers using the memory-mapped interface, when
PADDRDBG31 is LOW.
When the software lock is set, write accesses using the memory-mapped
interface to all ETM trace unit registers are ignored, except for write
accesses to the TRCLAR.
When the software lock is set, read accesses of TRCPDSR do not change
the TRCPDSR.STICKYPD bit. Read accesses of all other registers are not
affected.
Usage constraints Accessible only from the memory-mapped interface.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-59 shows the TRCLAR bit assignments.
Figure 13-59 TRCLAR bit assignments
Table 13-61 shows the TRCLAR bit assignments.
The TRCLAR can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFB0
.
13.8.59 Software Lock Status Register
The TRCLSR characteristics are:
Purpose Determines whether the software lock is implemented, and indicates the
current status of the software lock.
Usage constraints Accessible only from the memory-mapped interface or the external
debugger interface.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
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