ARM Cortex-A53 MPCore - Page 569

Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-74
ID021414 Non-Confidential
Table 13-75 shows the TRCCIDR1 bit assignments.
The TRCCIDR1 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFF4 .
Component Identification Register 2
The TRCCIDR2 characteristics are:
Purpose Provides information to identify a CTI component.
Usage constraints • Only bits[7:0] are valid.
• Accessible only from the memory-mapped interface or the external
debugger interface.
Configurations Available in all implementations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-72 shows the TRCCIDR2 bit assignments.
Figure 13-72 TRCCIDR2 bit assignments
Table 13-76 shows the TRCCIDR2 bit assignments.
The TRCCIDR2 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFF8 .
Component Identification Register 3
The TRCCIDR3 characteristics are:
Purpose Provides information to identify a trace component.
Usage constraints • Only bits[7:0] are valid.
• Accessible only from the memory-mapped interface or the external
debugger interface.
Table 13-75 TRCCIDR1 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0
[7:4] CLASS
0x9 Debug component
[3:0] PRMBL_1
0x0 Preamble byte 1
RES0
31 0
PRMBL_2
78
Table 13-76 TRCCIDR2 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:0] PRMBL_2
0x05 Preamble byte 2.