ARM Cortex-A53 MPCore - Page 568

Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-73
ID021414 Non-Confidential
Usage constraints • Only bits[7:0] are valid.
• Accessible only from the memory-mapped interface or the external
debugger interface.
Configurations Available in all implementations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-70 shows the TRCCIDR0 bit assignments.
Figure 13-70 TRCCIDR0 bit assignments
Table 13-74 shows the TRCCIDR0 bit assignments.
The TRCCIDR0 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFF0 .
Component Identification Register 1
The TRCCIDR1 characteristics are:
Purpose Provides information to identify a trace component.
Usage constraints • Only bits[7:0] are valid.
• Accessible only from the memory-mapped interface or the external
debugger interface.
Configurations Available in all implementations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-71 shows the TRCCIDR1 bit assignments.
Figure 13-71 TRCCIDR1 bit assignments
RES0
31 0
PRMBL_0
78
Table 13-74 TRCCIDR0 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:0] PRMBL_0
0x0D Preamble byte 0.
RES0
31 0
PRMBL_1
78
34
CLASS