ARM Cortex-A53 MPCore - Page 567

Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-72
ID021414 Non-Confidential
Figure 13-69 TRCPIDR4 bit assignments
Table 13-72 shows the TRCPIDR4 bit assignments.
The TRCPIDR4 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFD0 .
Peripheral Identification Register 5-7
No information is held in the Peripheral ID5, Peripheral ID6 and Peripheral ID7 Registers. They
are reserved for future use and are
RES0.
13.8.65 Component Identification Registers
There are four read-only Component Identification Registers, Component ID0 to Component
ID3. Table 13-73 shows these registers.
The Component Identification Registers identify ETM trace unit as a CoreSight component.
The Component ID registers are:
• Component Identification Register 0.
• Component Identification Register 1 on page 13-73.
• Component Identification Register 2 on page 13-74.
• Component Identification Register 3 on page 13-74.
Component Identification Register 0
The TRCCIDR0 characteristics are:
Purpose Provides information to identify a trace component.
RES0
31 0
34
DES_2
78
Size
Table 13-72 TRCPIDR4 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:4] Size
0x0 Size of the component. Log2 the number of 4KB pages from the start of the component to the end
of the component ID registers.
[3:0] DES_2
0x4 ARM Limited. This is bits [3:0] of the JEP106 continuation code.
Table 13-73 Summary of the Component Identification Registers
Register Value Offset
Component ID0
0x0D 0xFF0
Component ID1 0x90 0xFF4
Component ID2 0x05 0xFF8
Component ID3 0xB1 0xFFC