ARM Cortex-A53 MPCore - Page 566

Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-71
ID021414 Non-Confidential
The TRCPIDR2 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFE8 .
Peripheral Identification Register 3
The TRCPIDR3 characteristics are:
Purpose Provides information to identify a trace component.
Usage constraints • Only bits[7:0] are valid.
• Accessible only from the memory-mapped interface or the external
debugger interface.
Configurations Available in all implementations.
Attributes TRCPIDR3 is a 32-bit RO management register.
See the register summary in Table 13-3 on page 13-10.
Figure 13-68 shows the TRCPIDR3 bit assignments.
Figure 13-68 TRCPIDR3 bit assignments
Table 13-71 shows the TRCPIDR3 bit assignments.
The TRCPIDR3 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFEC .
Peripheral Identification Register 4
The TRCPIDR4 characteristics are:
Purpose Provides information to identify a trace component.
Usage constraints • Only bits[7:0] are valid.
• Accessible only from the memory-mapped interface or the external
debugger interface.
Configurations Available in all implementations.
Attributes TRCPIDR4 is a 32-bit RO management register.
See the register summary in Table 13-3 on page 13-10.
Figure 13-69 on page 13-72 shows the TRCPIDR4 bit assignments.
RES0
31 0
34
CMOD
78
REVAND
Table 13-71 TRCPIDR3 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:4] REVAND
0x0 Part minor revision.
[3:0] CMOD
0x0 Not customer modified.