ARM Cortex-A53 MPCore - Page 565

Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-70
ID021414 Non-Confidential
Figure 13-66 TRCPIDR1 bit assignments
Table 13-69 shows the TRCPIDR1 bit assignments.
The TRCPIDR1 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFE4 .
Peripheral Identification Register 2
The TRCPIDR2 characteristics are:
Purpose Provides information to identify a trace component.
Usage constraints • Only bits[7:0] are valid.
• Accessible only from the memory-mapped interface or the external
debugger interface.
Configurations Available in all implementations.
Attributes TRCPIDR2 is a 32-bit RO management register.
See the register summary in Table 13-3 on page 13-10.
Figure 13-67 shows the TRCPIDR2 bit assignments.
Figure 13-67 TRCPIDR2 bit assignments
Table 13-70 shows the TRCPIDR2 bit assignments.
RES0
31 0
34
Part_1
78
DES_0
Table 13-69 TRCPIDR1 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:4] DES_0
0xB ARM Limited. This is bits [3:0] of JEP106 ID code.
[3:0] Part_1
0x9 Most significant four bits of the ETM trace unit part number.
RES 0
31 0
34
DES_1
78
Revision
JEDEC
2
Table 13-70 TRCPIDR2 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:4] Revision
0x2 r0p2.
[3] JEDEC
0b1 RES1. Indicates a JEP106 identity code is used.
[2:0] DES_1
0b011 ARM Limited. This is bits [6:4] of JEP106 ID code.