Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-69
ID021414 Non-Confidential
The Peripheral ID registers are:
• Peripheral Identification Register 0.
• Peripheral Identification Register 1.
• Peripheral Identification Register 2 on page 13-70.
• Peripheral Identification Register 3 on page 13-71.
• Peripheral Identification Register 4 on page 13-71.
• Peripheral Identification Register 5-7 on page 13-72.
Peripheral Identification Register 0
The TRCPIDR0 characteristics are:
Purpose Provides information to identify a trace component.
Usage constraints • Only bits[7:0] are valid.
• Accessible only from the memory-mapped interface or the external
debugger interface, offset
0xFE0
.
Configurations Available in all implementations.
Attributes TRCPIDR0 is a 32-bit RO management register.
See the register summary in Table 13-3 on page 13-10.
Figure 13-65 shows the TRCPIDR0 bit assignments.
Figure 13-65 TRCPIDR0 bit assignments
Table 13-68 shows the TRCPIDR0 bit assignments.
Peripheral Identification Register 1
The TRCPIDR1 characteristics are:
Purpose Provides information to identify a trace component.
Usage constraints • Only bits[7:0] are valid.
• Accessible only from the memory-mapped interface or the external
debugger interface.
Configurations Available in all implementations.
Attributes TRCPIDR1 is a 32-bit RO management register.
See the register summary in Table 13-3 on page 13-10.
Figure 13-66 on page 13-70 shows the TRCPIDR1 bit assignments.
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