ARM Cortex-A53 MPCore - Page 563

Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-68
ID021414 Non-Confidential
Usage constraints Accessible only from the memory-mapped interface or the external
debugger interface.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-64 shows the TRCDEVTYPE bit assignments.
Figure 13-64 TRCDEVTYPE bit assignments
Table 13-66 shows the TRCDEVTYPE bit assignments.
The TRCDEVTYPE can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFCC .
13.8.64 Peripheral Identification Registers
The Peripheral Identification Registers provide standard information required for all CoreSight
components. They are a set of eight registers, listed in register number order in Table 13-67.
Only bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, the
eight Peripheral ID Registers define a single 64-bit Peripheral ID.
SUB MAJORRES0
31 0
4378
Table 13-66 TRCDEVTYPE bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:4] SUB The sub-type of the component:
b0001 Processor trace.
[3:0] MAJOR The main type of the component:
b0011 Trace source.
Table 13-67 Summary of the Peripheral ID Registers
Register Value Offset
Peripheral ID4
0x04 0xFD0
Peripheral ID5 0x00 0xFD4
Peripheral ID6 0x00 0xFD8
Peripheral ID7 0x00 0xFDC
Peripheral ID0 0x5D 0xFE0
Peripheral ID1 0xB9 0xFE4
Peripheral ID2 0x2B 0xFE8
Peripheral ID3 0x00 0xFEC