ARM Cortex-A53 MPCore - Page 562

Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-67
ID021414 Non-Confidential
Table 13-64 shows the TRCDEVARCH bit assignments.
The TRCDEVARCH can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFBC .
13.8.62 Device ID Register
The TRCDEVID characteristics are:
Purpose Indicates the capabilities of the ETM trace unit.
Usage constraints There are no usage constraints.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-63 shows the TRCDEVID bit assignments.
Figure 13-63 TRCDEVID bit assignments
Table 13-65 shows the TRCDEVID bit assignments.
The TRCDEVID can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFC8 .
13.8.63 Device Type Register
The TRCDEVTYPE characteristics are:
Purpose Indicates the type of the component.
Table 13-64 TRCDEVARCH bit assignments
Bits Name Function
[31:21] ARCHITECT Defines the architect of the component:
0x4 ARM JEP continuation.
0x3B ARM JEP 106 code.
[20] PRESENT Indicates the presence of this register:
b1 Register is present.
[19:16] REVISION Architecture revision:
b0000 Architecture revision 0.
[15:0] ARCHID Architecture ID:
0x4A13 ETMv4 component.
DEVID
31 0
Table 13-65 TRCDEVID bit assignments
Bits Name Function
[31:0] DEVID RAZ. There are no component-defined capabilities.