Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-66
ID021414 Non-Confidential
Table 13-63 shows the TRCAUTHSTATUS bit assignments.
The TRCAUTHSTATUS can be accessed through the internal memory-mapped interface and
the external debug interface, offset
0xFB8
.
13.8.61 Device Architecture Register
The TRCDEVARCH characteristics are:
Purpose Identifies the ETM trace unit as an ETMv4 component.
Usage constraints There are no usage constraints.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-62 shows the TRCDEVARCH bit assignments.
Figure 13-62 TRCDEVARCH bit assignments
Table 13-63 TRCAUTHSTATUS bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:6] SNID Secure Non-invasive Debug:
b10
Secure Non-invasive Debug implemented but disabled.
b11
Secure Non-invasive Debug implemented and enabled.
[5:4] SID Secure Invasive Debug:
b00
Secure Invasive Debug is not implemented.
[3:2] NSNID Non-secure Non-invasive Debug:
b10
Non-secure Non-invasive Debug implemented but disabled, NIDEN=0.
b11
Non-secure Non-invasive Debug implemented and enabled, NIDEN=1.
[1:0] NSID Non-secure Invasive Debug:
b00
Non-secure Invasive Debug is not implemented.
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