ARM Cortex-A53 MPCore - Page 577

Cross Trigger
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-6
ID021414 Non-Confidential
0x13C CTICHOUTSTATUS RO CTI Channel Out Status Register
0x140 CTIGATE RW CTI Channel Gate Enable Register
0x144 ASICCTL RW CTI External Multiplexer Control Register
0x148-0xF7C --Reserved
0xF00 CTIITCTRL RW CTI Integration Mode Control Register on page 14-9
0xF04-0xFA4 --Reserved
0xFA0 CTICLAIMSET RW CTI Claim Tag Set Register
0xFA4 CTICLAIMCLR RW CTI Claim Tag Clear Register
0xFA8 CTIDEVAFF0 RO CTI Device Affinity Register 0
0xFAC CTIDEVAFF1 RO CTI Device Affinity Register 1
0xFB0 CTILAR WO CTI Lock Access Register
0xFB4 CTILSR RO CTI Lock Status Register
0xFB8 CTIAUTHSTATUS RO CTI Authentication Status Register
0xFBC CTIDEVARCH RO CTI Device Architecture Register
0xFC0 CTIDEVID2 RO CTI Device ID Register 2
0xFC4 CTIDEVID1 RO CTI Device ID Register 1
0xFC8 CTIDEVID RO CTI Device Identification Register on page 14-8
0xFCC CTIDEVTYPE RO CTI Device Type Register
0xFD0 CTIPIDR4 RO Peripheral Identification Register 4 on page 14-13
0xFD4 CTIPIDR5 RO Peripheral Identification Register 5-7 on page 14-14
0xFD8 CTIPIDR6 RO
0xFDC CTIPIDR7 RO
0xFE0 CTIPIDR0 RO Peripheral Identification Register 0 on page 14-10
0xFE4 CTIPIDR1 RO Peripheral Identification Register 1 on page 14-11
0xFE8 CTIPIDR2 RO Peripheral Identification Register 2 on page 14-12
0xFEC CTIPIDR3 RO Peripheral Identification Register 3 on page 14-12
0xFF0 CTICIDR0 RO Component Identification Register 0 on page 14-14
0xFF4 CTICIDR1 RO Component Identification Register 1 on page 14-15
0xFF8 CTICIDR2 RO Component Identification Register 2 on page 14-16
0xFFC CTICIDR3 RO Component Identification Register 3 on page 14-17
Table 14-3 Cross trigger register summary (continued)
Offset Name Type Description