Cross Trigger
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-7
ID021414 Non-Confidential
14.4.1 External register access permissions
External access permission to the cross trigger registers is subject to the conditions at the time
of the access. Table 14-4 describes the processor response to accesses through the external
debug and memory-mapped interfaces.
Table 14-5 shows an example of external register condition codes for access to a cross trigger
register. To determine the access permission for the register, scan the columns from left to right.
Stop at the first column a condition is true, the entry gives the access permission of the register
and scanning stops.
Table 14-4 External register conditions
Name Condition Description
Off EDPRSR.PU is 0 Processor power domain is completely off, or in a low-power state where the
processor power domain registers cannot be accessed.
DLK EDPRSR.DLK is 1 OS Double Lock is locked.
OSLK OSLSR_EL1.OSLK is 1 OS Lock is locked.
EDAD
AllowExternalDebugAccess() ==FALSE
External debug access is disabled. When an error is returned because of an EDAD
condition code, and this is the highest priority error condition, EDPRSR.SDAD is
set to 1. Otherwise EDPRSR.SDAD is unchanged.
SLK Memory-mapped interface only Software lock is locked. For the external debug interface, ignore this row.
Default - None of the conditions apply, normal access.
Table 14-5 External register condition code example
Off DLK OSLK EDAD SLK Default
-- - - RO/WIRO
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