ARM Cortex-A53 MPCore - Page 580

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ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-9
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CTIDEVID can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFC8 .
14.5.2 CTI Integration Mode Control Register
The CTIITCTRL characteristics are:
Purpose The CTIITCTRL shows that the Cortex-A53 processor does not
implement an integration mode.
Usage constraints The accessibility of CTIITCTRL by condition code is:
Table 14-4 on page 14-7 describes the condition codes.
Configurations CTIITCTRL is in the Debug power domain.
Attributes See the register summary in Table 14-3 on page 14-5.
Figure 14-3 shows the CTIITCTRL bit assignments.
Figure 14-3 CTIITCTRL bit assignments
Table 14-7 shows the CTIITCTRL bit assignments.
CTIITCTRL can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xF00 .
Off DLK OSLK EDAD SLK Default
-- - - RO/WIRW
31 0
1
RES0
IME
Table 14-7 CTIITCTRL bit assignments
Bits Name Function
[31:1] - Reserved,
RES0.
[0] IME Integration mode enable. The possible value is:
0 Normal operation.