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ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-10
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14.5.3 CTI Peripheral Identification Registers
The Peripheral Identification Registers provide standard information required for all
components that conform to the ARM CoreSight architecture. There is a set of eight registers,
listed in register number order in Table 14-8.
Only bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, the
eight Peripheral ID Registers define a single 64-bit Peripheral ID.
The Peripheral ID registers are:
• Peripheral Identification Register 0.
• Peripheral Identification Register 1 on page 14-11.
• Peripheral Identification Register 2 on page 14-12.
• Peripheral Identification Register 3 on page 14-12.
• Peripheral Identification Register 4 on page 14-13.
• Peripheral Identification Register 5-7 on page 14-14.
Peripheral Identification Register 0
The CTIPIDR0 characteristics are:
Purpose Provides information to identify a CTI component.
Usage constraints The accessibility of CTIPIDR0 by condition code is:
Table 14-4 on page 14-7 describes the condition codes.
Configurations CTIPIDR0 is in the Debug power domain.
CTIPIDR0 is optional to implement in the external register interface.
Attributes See the register summary in Table 14-3 on page 14-5.
Figure 14-4 on page 14-11 shows the CTIPIDR0 bit assignments.
Table 14-8 Summary of the Peripheral Identification Registers
Register Value Offset
Peripheral ID4
0x04 0xFD0
Peripheral ID5
0x00 0xFD4
Peripheral ID6
0x00 0xFD8
Peripheral ID7
0x00 0xFDC
Peripheral ID0
0xA8 0xFE0
Peripheral ID1
0xB9 0xFE4
Peripheral ID2
0x2B 0xFE8
Peripheral ID3
0x00 0xFEC
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
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