ARM Cortex-A53 MPCore - Page 582

Cross Trigger
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-11
ID021414 Non-Confidential
Figure 14-4 CTIPIDR0 bit assignments
Table 14-9 shows the CTIPIDR0 bit assignments.
CTIPIDR0 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFE0 .
Peripheral Identification Register 1
The CTIPIDR1 characteristics are:
Purpose Provides information to identify a CTI component.
Usage constraints The accessibility of CTIPIDR1 by condition code is:
Table 14-4 on page 14-7 describes the condition codes.
Configurations CTIPIDR1 is in the Debug power domain.
CTIPIDR1 is optional to implement in the external register interface.
Attributes See the register summary in Table 14-3 on page 14-5.
Figure 14-5 shows the CTIPIDR1 bit assignments.
Figure 14-5 CTIPIDR1 bit assignments
Table 14-10 shows the CTIPIDR1 bit assignments.
RES0
31 0
78
Part_0
Table 14-9 CTIPIDR0 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:0] Part_0
0xA8 Least significant byte of the cross trigger part number.
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
RES0
31 0
34
Part_1
78
DES_0
Table 14-10 CTIPIDR1 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:4] DES_0
0xB ARM Limited. This is the least significant nibble of JEP106 ID code.
[3:0] Part_1
0x9 Most significant nibble of the CTI part number.