Cross Trigger
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-12
ID021414 Non-Confidential
CTIPIDR1 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFE4
.
Peripheral Identification Register 2
The CTIPIDR2 characteristics are:
Purpose Provides information to identify a CTI component.
Usage constraints The accessibility of CTIPIDR2 by condition code is:
Table 14-4 on page 14-7 describes the condition codes.
Configurations CTIPIDR2 is in the Debug power domain.
CTIPIDR2 is optional to implement in the external register interface.
Attributes See the register summary in Table 14-3 on page 14-5.
Figure 14-6 shows the CTIPIDR2 bit assignments.
Figure 14-6 CTIPIDR2 bit assignments
Table 14-11 shows the CTIPIDR2 bit assignments.
CTIPIDR2 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFE8
.
Peripheral Identification Register 3
The CTIPIDR3 characteristics are:
Purpose Provides information to identify a CTI component.
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 14-11 CTI PIDR2 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:4] Revision
0x2
r0p2.
[3] JEDEC
0b1
RES1. Indicates a JEP106 identity code is used.
[2:0] DES_1
0b011
ARM Limited. This is the most significant nibble of JEP106 ID code.
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