Cross Trigger
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-13
ID021414 Non-Confidential
Usage constraints The accessibility of CTIPIDR3 by condition code is:
Table 14-4 on page 14-7 describes the condition codes.
Configurations CTIPIDR3 is in the Debug power domain.
CTIPIDR3 is optional to implement in the external register interface.
Attributes See the register summary in Table 14-3 on page 14-5.
Figure 14-7 shows the CTIPIDR3 bit assignments.
Figure 14-7 CTIPIDR3 bit assignments
Table 14-12 shows the CTIPIDR3 bit assignments.
CTIPIDR3 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFEC
.
Peripheral Identification Register 4
The CTIPIDR4 characteristics are:
Purpose Provides information to identify a CTI component.
Usage constraints The accessibility of CTIPIDR4 by condition code is:
Table 14-4 on page 14-7 describes the condition codes.
Configurations CTIPIDR4 is in the Debug power domain.
CTIPIDR4 is optional to implement in the external register interface.
Attributes See the register summary in Table 14-3 on page 14-5.
Figure 14-8 on page 14-14 shows the CTIPIDR4 bit assignments.
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
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