Cross Trigger
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-15
ID021414 Non-Confidential
Usage constraints The accessibility of CTICIDR0 by condition code is:
Table 14-4 on page 14-7 describes the condition codes.
Configurations CTICIDR0 is in the Debug power domain.
CTICIDR0 is optional to implement in the external register interface.
Attributes See the register summary in Table 14-3 on page 14-5.
Figure 14-9 shows the CTICIDR0 bit assignments.
Figure 14-9 CTICIDR0 bit assignments
Table 14-15 shows the CTICIDR0 bit assignments.
CTICIDR0 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFF0
.
Component Identification Register 1
The CTICIDR1 characteristics are:
Purpose Provides information to identify a CTI component.
Usage constraints The accessibility of CTICIDR1 by condition code is:
Table 14-4 on page 14-7 describes the condition codes.
Configurations CTICIDR1 is in the Debug power domain.
CTICIDR1 is optional to implement in the external register interface.
Attributes See the register summary in Table 14-3 on page 14-5.
Figure 14-10 on page 14-16 shows the CTICIDR1 bit assignments.
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
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