ARM Cortex-A53 MPCore - Page 587

Cross Trigger
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 14-16
ID021414 Non-Confidential
Figure 14-10 CTICIDR1 bit assignments
Table 14-16 shows the CTICIDR1 bit assignments.
CTICIDR1 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFF4 .
Component Identification Register 2
The CTICIDR2 characteristics are:
Purpose Provides information to identify a CTI component.
Usage constraints The accessibility of CTICIDR2 by condition code is:
Table 14-4 on page 14-7 describes the condition codes.
Configurations CTICIDR2 is in the Debug power domain.
CTICIDR2 is optional to implement in the external register interface.
Attributes See the register summary in Table 14-3 on page 14-5.
Figure 14-11 shows the CTICIDR2 bit assignments.
Figure 14-11 CTICIDR2 bit assignments
Table 14-17 shows the CTICIDR2 bit assignments.
RES0
31 0
PRMBL_1
78
34
CLASS
Table 14-16 CTICIDR1 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:4] CLASS
0x9 Debug component.
[3:0] PRMBL_1
0x0 Preamble byte 1.
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
RES0
31 0
PRMBL_2
78
Table 14-17 CTICIDR2 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:0] PRMBL_2
0x05 Preamble byte 2.