Cortex-A53 Processor AArch32 unpredictable Behaviors
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. B-6
ID021414 Non-Confidential
B.4 ARMv8 Debug UNPREDICTABLE behaviors
The ARMv8 Debug Implementation Envelope architectural reference document describes
UNPREDICTABLE behaviors associated with Debug. Some topics list behavior Options and many
include a Preference behavior. For any particular topics that have multiple options, the
information in this section describes which option the Cortex-A53 processor implements.
Additionally, for any particular topics for which the Cortex-A53 processor behavior diverges
from either or both of the Options and Preferences, an explanation of the actual behavior is
given. If there is only a single Option for a specific topic in ARMv8 Debug Implementation
Envelope, if the Cortex-A53 processor follows the recommended behavior, then there are no
more explanatory comments in this appendix for that topic or behavior.
B.4.1 A32 BKPT instruction with condition code not AL
The Cortex-A53 processor implements the preferred option:
• Option 3: executed unconditionally.
B.4.2 Address match breakpoint match only on second halfword of an instruction
The Cortex-A53 processor generates a breakpoint on the instruction, unless it is a breakpoint on
the second half of the first 32-bit instruction. In this case the breakpoint is taken on the following
instruction.
B.4.3 Address matching breakpoint on A32 instruction with DBGBCRn.BAS=1100
The Cortex-A53 processor implements:
• Option 1: Does match.
B.4.4 Address match breakpoint match on T32 instruction at DBGBCRn+2 with DBGBCRn.BAS=1111
The Cortex-A53 processor implements:
• Option 1: Does match.
B.4.5 Address mismatch breakpoint match on T32 instruction at DBGBCRn +2 with
DBGBCRn.BAS=1111
The Cortex-A53 processor implements:
• Option 1: Does match.
B.4.6 Other mismatch breakpoint matches any address in current mode and state
The Cortex-A53 processor implements:
• Option 2: Immediate breakpoint debug event.
B.4.7 Mismatch breakpoint on branch to self
The Cortex-A53 processor implements:
• Option 2: Instruction is stepped an
UNKNOWN number of times, while it continues to
branch to itself.
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