Cortex-A53 Processor AArch32 unpredictable Behaviors
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. B-7
ID021414 Non-Confidential
B.4.8 Link to nonexistent breakpoint or breakpoint that is not context-aware
The Cortex-A53 processor implements:
• Option 1: No Breakpoint or Watchpoint debug event is generated, and the LBN field of
the linker reads
UNKNOWN.
B.4.9 DBGWCRn_EL1.MASK!=00000 and DBGWCRn_EL1.BAS!=11111111
The Cortex-A53 processor behaves as indicated in the sole Preference:
• DBGWCRn_EL1.BAS is ignored and treated as if
0b11111111
B.4.10 Address-matching Vector catch on 32-bit T32 instruction at (vector-2)
The Cortex-A53 processor implements:
• Option 1: Does match.
B.4.11 Address-matching Vector catch on 32-bit T32 instruction at (vector+2)
The Cortex-A53 processor implements:
• Option 1: Does match.
B.4.12 Address-matching Vector catch and Breakpoint on same instruction
The Cortex-A53 processor implements:
• Option 2: Report Breakpoint.
B.4.13 Address match breakpoint with DBGBCRn_EL1.BAS=0000
The Cortex-A53 processor implements:
• Option 1. As if disabled.
B.4.14 DBGWCRn_EL1.BAS specifies a non-contiguous set of bytes within a double-word
The Cortex-A53 processor implements:
• A Watchpoint debug event is generated for each byte.
B.4.15 A32 HLT instruction with condition code not AL
The Cortex-A53 processor implements:
• Option 3. Executed unconditionally.
B.4.16 Execute instruction at a given EL when the corresponding EDECCR bit is 1 and Halting is allowed
The Cortex-A53 processor behaves as follows:
• Generates debug event and Halt no later than the instruction following the next Context
Synchronization operation (CSO) excluding ISB instruction.
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