ARM Cortex-A53 MPCore - Page 66

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4.2.2 AArch64 exception handling registers
Table 4-2 shows the fault handling registers in AArch64 state. Bits[63:32] are reset to
0x00000000 for all 64-bit registers in Table 4-2.
Table 4-2 AArch64 exception handling registers
Name Type Reset Width Description
AFSR0_EL1 RW
0x00000000 32 Auxiliary Fault Status Register 0, EL1, EL2 and EL3 on page 4-97
AFSR1_EL1 RW
0x00000000 32 Auxiliary Fault Status Register 1, EL1, EL2 and EL3 on page 4-97
ESR_EL1 RW UNK 32 Exception Syndrome Register, EL1 on page 4-97
IFSR32_EL2 RW UNK 32 Instruction Fault Status Register, EL2 on page 4-98
AFSR0_EL2 RW
0x00000000 32 Auxiliary Fault Status Register 0, EL1, EL2 and EL3 on page 4-97
AFSR1_EL2 RW
0x00000000 32 Auxiliary Fault Status Register 1, EL1, EL2 and EL3 on page 4-97
ESR_EL2 RW UNK 32 Exception Syndrome Register, EL2 on page 4-101
AFSR0_EL3 RW
0x00000000 32 Auxiliary Fault Status Register 0, EL1, EL2 and EL3 on page 4-97
AFSR1_EL3 RW
0x00000000 32 Auxiliary Fault Status Register 1, EL1, EL2 and EL3 on page 4-97
ESR_EL3 RW UNK 32 Exception Syndrome Register, EL3 on page 4-102
FAR_EL1 RW UNK 64 Fault Address Register, EL1 on page 4-103
FAR_EL2 RW UNK 64 Fault Address Register, EL2 on page 4-104
HPFAR_EL2 RW
0x00000000 64 Hypervisor IPA Fault Address Register, EL2 on page 4-105
FAR_EL3 RW UNK 64 Fault Address Register, EL3 on page 4-111
VBAR_EL1 RW UNK 64 Vector Base Address Register, EL1 on page 4-119
ISR_EL1 RO UNK 32 Interrupt Status Register on page 4-123
VBAR_EL2 RW UNK 64 Vector Base Address Register, EL2 on page 4-120
VBAR_EL3 RW UNK 64 Vector Base Address Register, EL3 on page 4-121