ARM Cortex-A53 MPCore - Page 67

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-6
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4.2.3 AArch64 virtual memory control registers
Table 4-3 shows the virtual memory control registers in AArch64 state. Bits[63:32] are reset to
0x00000000 for all 64-bit registers in Table 4-3.
Table 4-3 AArch64 virtual memory control registers
Name Type Reset Width Description
SCTLR_EL1 RW
0x00C50838
a
32 System Control Register, EL1 on page 4-50
SCTLR_EL2 RW
0x30C50838
b
32 System Control Register, EL2 on page 4-58
SCTLR_EL3 RW
0x00C50838
a
32 System Control Register, EL3 on page 4-74
TTBR0_EL1 RW UNK 64 Translation Table Base Register 0, EL1 on page 4-79
TTBR1_EL1 RW UNK 64 Translation Table Base Register 1 on page 4-80
TCR_EL1 RW UNK 64 Translation Control Register, EL1 on page 4-86
TTBR0_EL2 RW UNK 64
Translation Table Base Address Register 0, EL2
c
TCR_EL2 RW UNK 32 Translation Control Register, EL2 on page 4-89
VTTBR_EL2 RW UNK 64
Virtualization Translation Table Base Address Register, EL2
c
VTCR_EL2 RW UNK 32 Virtualization Translation Control Register, EL2 on page 4-91
TTBR0_EL3 RW UNK 64 Translation Table Base Register 0, EL3 on page 4-93
TCR_EL3 RW UNK 32 Translation Control Register, EL3 on page 4-94
MAIR_EL1 RW UNK 64 Memory Attribute Indirection Register, EL1 on page 4-116
AMAIR_EL1 RW 0x00000000 64 Auxiliary Memory Attribute Indirection Register, EL1, EL2 and EL3 on
page 4-97
MAIR_EL2 RW UNK 64 Memory Attribute Indirection Register, EL2 on page 4-118
AMAIR_EL2 RW
0x00000000 64 Auxiliary Memory Attribute Indirection Register, EL1, EL2 and EL3 on
page 4-97
MAIR_EL3 RW UNK 64 Memory Attribute Indirection Register, EL3 on page 4-118
AMAIR_EL3 RW
0x00000000 64 Auxiliary Memory Attribute Indirection Register, EL1, EL2 and EL3 on
page 4-97
CONTEXTIDR_EL1 RW UNK 32
Context ID Register, EL1
c
a. The reset value depends on primary inputs CFGTE and CFGEND. Table 4-3 assumes these signals are LOW.
b. The reset value depends on primary inputs CFGTE, CFGEND and VINITHI. Table 4-3 assumes these signals are LOW.
c. See the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.