ARM Cortex-A53 MPCore - Page 68

System Control
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4.2.4 AArch64 other system control registers
Table 4-4 shows the other system control registers in AArch64 state.
4.2.5 AArch64 performance monitor registers
Table 4-5 shows the performance monitor registers in AArch64 state. Bits[63:32] are reset to
0x00000000 for all 64-bit registers in Table 4-5.
Table 4-4 AArch64 other system control registers
Name Type Reset Width Description
ACTLR_EL1 RW
0x00000000 32 Auxiliary Control Register, EL1 on page 4-55
CPACR_EL1 RW
0x00000000 32 Architectural Feature Access Control Register on page 4-57
ACTLR_EL2 RW
0x00000000 32 Auxiliary Control Register, EL2 on page 4-55
ACTLR_EL3 RW
0x00000000 32 Auxiliary Control Register, EL3 on page 4-56
Table 4-5 AArch64 performance monitor registers
Name Type Reset Width Description
PMCR_EL0 RW
0x41033000 32 Performance Monitors Control Register on page 12-7
PMCNTENSET_EL0 RW UNK 32
Performance Monitors Count Enable Set Register
a
PMCNTENCLR_EL0 RW UNK 32
Performance Monitors Count Enable Clear Register
a
PMOVSCLR_EL0 RW UNK 32
Performance Monitors Overflow Flag Status Clear Register
a
PMSWINC_EL0 WO - 32
Performance Monitors Software Increment Register
a
PMSELR_EL0 RW UNK 32
Performance Monitors Event Counter Selection Register
a
PMCEID0_EL0 RO
0x67FFBFFF
b
32 Performance Monitors Common Event Identification Register 0 on
page 12-9
PMCEID1_EL0 RO
0x00000000 32 Performance Monitors Common Event Identification Register 1 on
page 12-12
a
PMCCNTR_EL0 RW UNK 64
Performance Monitors Cycle Counter
a
PMXEVTYPER_EL0 RW UNK 32
Performance Monitors Selected Event Type and Filter Register
a
PMXEVCNTR_EL0 RW UNK 32
Performance Monitors Selected Event Counter Register
a
PMUSERENR_EL0 RW 0x00000000 32
Performance Monitors User Enable Register
a
PMINTENSET_EL1 RW UNK 32
Performance Monitors Interrupt Enable Set Register
a
PMINTENCLR_EL1 RW UNK 32
Performance Monitors Interrupt Enable Clear Register
a
PMOVSSET_EL0 RW UNK 32
Performance Monitors Overflow Flag Status Set Register
a