ARM Cortex-A53 MPCore - Page 69

System Control
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4.2.6 AArch64 reset registers
Table 4-6 shows the reset registers in AArch64 state.
PMEVCNTR0_EL0 RW UNK 32 Performance Monitor Event Count Registers
PMEVCNTR1_EL0 RW UNK 32
PMEVCNTR2_EL0 RW UNK 32
PMEVCNTR3_EL0 RW UNK 32
PMEVCNTR4_EL0 RW UNK 32
PMEVCNTR5_EL0 RW UNK 32
PMEVTYPER0_EL0 RW UNK 32 Performance Monitor Event Type Registers
PMEVTYPER1_EL0 RW UNK 32
PMEVTYPER2_EL0 RW UNK 32
PMEVTYPER3_EL0 RW UNK 32
PMEVTYPER4_EL0 RW UNK 32
PMEVTYPER5_EL0 RW UNK 32
PMCCFILTR_EL0 RW
0x00000000 32
Performance Monitors Cycle Count Filter Register
a
a. See the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.
b. The reset value is
0x663FBFFF if the Cortex-A53 processor has not been configured with an L2 cache.
Table 4-5 AArch64 performance monitor registers (continued)
Name Type Reset Width Description
Table 4-6 AArch64 reset management registers
Name Type Reset Width Description
RVBAR_EL3 RO
-
a
64 Reset Vector Base Address Register, EL3 on page 4-121
RMR_EL3 RW
0x00000001 32 Reset Management Register on page 4-122
a. The reset value depends on the RVBARADDR signal.