ARM Cortex-A53 MPCore - Page 70

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-9
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4.2.7 AArch64 secure registers
Table 4-7 shows the secure registers in AArch64 state.
4.2.8 AArch64 virtualization registers
Table 4-8 shows the virtualization registers in AArch64 state. Bits[63:32] are reset to
0x00000000
for all 64-bit registers in Table 4-8.
Table 4-7 AArch64 security registers
Name Type Reset Width Description
SCR_EL3 RW
0x00000000 32 Secure Configuration Register on page 4-76
SDER32_EL3 RW
0x00000000 32 Secure Debug Enable Register on page 4-78
CPTR_EL3 RW
0x00000000
a
32 Architectural Feature Trap Register, EL3 on page 4-81
MDCR_EL3 RW 0x00000000 32 Monitor Debug Configuration Register, EL3 on page 4-82
AFSR0_EL3 RW
0x00000000 32 Auxiliary Fault Status Register 0, EL1, EL2 and EL3 on page 4-97
AFSR1_EL3 RW
0x00000000 32 Auxiliary Fault Status Register 1, EL1, EL2 and EL3 on page 4-97
VBAR_EL3 RW
0x0000000000000000 64 Vector Base Address Register, EL3 on page 4-121
a. Reset value is 0x00000000 if Advanced SIMD and Floating point are implemented, 0x00000400 otherwise.
Table 4-8 AArch64 virtualization registers
Name Type Reset Width Description
VPIDR_EL2 RW
0x410FD031 32 Virtualization Processor ID Register on page 4-49
VMPIDR_EL2 RW
-
a
64 Virtualization Multiprocessor ID Register on page 4-50
SCTLR_EL2 RW
0x30C50838
b
32 System Control Register, EL2 on page 4-58
ACTLR_EL2 RW
0x00000000 32 Auxiliary Control Register, EL2 on page 4-55
HCR_EL2 RW
0x00000000 64 Hypervisor Configuration Register on page 4-60
MDCR_EL2 RW
0x00000006 32 Hyp Debug Control Register on page 4-66
CPTR_EL2 RW
0x000033FF
c
32 Architectural Feature Trap Register, EL2 on page 4-69
HSTR_EL2 RW
0x00000000 32 Hyp System Trap Register on page 4-70
HACR_EL2 RW
0x00000000 32 Hyp Auxiliary Configuration Register on page 4-74
TTBR0_EL2 RW UNK 64
Translation Table Base Address Register 0, EL3
d
TCR_EL2 RW UNK 32 Translation Control Register, EL2 on page 4-89
VTTBR_EL2 RW UNK 64
Virtualization Translation Table Base Address Register, EL2
d