ARM Cortex-A53 MPCore - Page 71

System Control
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4.2.9 AArch64 GIC system registers
Table 4-9 shows the GIC system registers in AArch64 state. See the ARM
®
Architecture
Reference Manual ARMv8, for ARMv8-A architecture profile for more information.
VTCR_EL2 RW UNK 32 Virtualization Translation Control Register, EL2 on page 4-91
DACR32_EL2 RW UNK 32 Domain Access Control Register on page 4-92
AFSR0_EL2 RW 0x00000000 32 Auxiliary Fault Status Register 0, EL1, EL2 and EL3 on page 4-97
AFSR1_EL2 RW
0x00000000 32 Auxiliary Fault Status Register 1, EL1, EL2 and EL3 on page 4-97
ESR_EL2 RW UNK 32 Exception Syndrome Register, EL2 on page 4-101
FAR_EL2 RW UNK 64 Fault Address Register, EL2 on page 4-104
HPFAR_EL2 RW UNK 64 Hypervisor IPA Fault Address Register, EL2 on page 4-105
MAIR_EL2 RW UNK 64 Memory Attribute Indirection Register, EL2 on page 4-118
AMAIR_EL2 RW
0x00000000 64 Auxiliary Memory Attribute Indirection Register, EL1, EL2 and EL3 on page 4-97
VBAR_EL2 RW UNK 64 Vector Base Address Register, EL2 on page 4-120
a. The reset value is the value of the Multiprocessor Affinity Register.
b. The reset value depends on inputs, CFGTE and CFGEND. The value shown assumes these signals are set to LOW.
c. Reset value is 0x0000BFFF if Advanced SIMD and Floating-point are not implemented.
d. See the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.
Table 4-8 AArch64 virtualization registers (continued)
Name Type Reset Width Description
Table 4-9 GIC system registers
Name Type Reset Width Description
ICC_AP0R0_EL1 RW
0x00000000 32 Active Priorities 0 Register 0
ICC_AP1R0_EL1 RW
0x00000000 32 Active Priorities 1 Register 0
ICC_ASGI1R_EL1 WO - 64 Alternate SGI Generation Register 1
ICC_BPR0_EL1 RW 0x00000002 32 Binary Point Register 0
ICC_BPR1_EL1 RW
0x00000003
a
32 Binary Point Register 1
ICC_CTLR_EL1 RW
0x00000400 32 Interrupt Control Register for EL1
ICC_CTLR_EL3 RW
0x00000400 32 Interrupt Control Register for EL3
ICC_DIR_EL1 WO - 32 Deactivate Interrupt Register
ICC_EOIR0_EL1 WO - 32 End Of Interrupt Register 0
ICC_EOIR1_EL1 WO - 32 End Of Interrupt Register 1
ICC_HPPIR0_EL1 RO - 32 Highest Priority Pending Interrupt Register 0
ICC_HPPIR1_EL1 RO - 32 Highest Priority Pending Interrupt Register 1
ICC_IAR0_EL1 RO - 32 Interrupt Acknowledge Register 0
ICC_IAR1_EL1 RO - 32 Interrupt Acknowledge Register 1