ARM Cortex-A53 MPCore - Page 72

System Control
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4.2.10 AArch64 Generic Timer registers
See Chapter 10 Generic Timer for information on the Generic Timer registers.
4.2.11 AArch64 thread registers
Table 4-10 shows the thread registers in AArch64 state. See the ARM
®
Architecture Reference
Manual ARMv8, for ARMv8-A architecture profile for more information about these operations.
ICC_IGRPEN0_EL1 RW 0x00000000 32 Interrupt Group Enable Register 0
ICC_IGRPEN1_EL1 RW
0x00000000 32 Interrupt Group Enable Register 1
ICC_IGRPEN1_EL3 RW
0x00000000 32 Interrupt Group Enable Register 1 for EL3
ICC_PMR_EL1 RW
0x00000000 32 Priority Mask Register
ICC_RPR_EL1 RO - 32 Running Priority Register
ICC_SEIEN_EL1 RW 0x00000000 32 System Error Interrupt Enable Register
ICC_SGI0R_EL1 WO - 64 SGI Generation Register 0
ICC_SGI1R_EL1 WO - 64 SGI Generation Register 1
ICC_SRE_EL1 RW
0x00000000 32 System Register Enable Register for EL1
ICC_SRE_EL2 RW
0x00000000 32 System Register Enable Register for EL2
ICC_SRE_EL3 RW
0x00000000 32 System Register Enable Register for EL3
a. This is the reset value in non-secure states. In secure states, the reset value is 0x00000002.
Table 4-9 GIC system registers (continued)
Name Type Reset Width Description
Table 4-10 AArch64 miscellaneous system control operations
Name Type Reset Width Description
TPIDR_EL0 RW UNK 64 Thread Pointer/ID Register, EL0
TPIDR_EL1 RW UNK 64 Thread Pointer/ID Register, EL1
TPIDRRO_EL0 RW UNK 64 Thread Pointer/ID Register, Read-Only, EL0
TPIDR_EL2 RW UNK 64 Thread Pointer/ID Register, EL2
TPIDR_EL3 RW UNK 64 Thread Pointer/ID Register, EL3