System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-16
ID021414 Non-Confidential
Table 4-15 shows the MPIDR_EL1 bit assignments.
To access the MPIDR_EL1:
MRS <Xt>, MPIDR_EL1 ; Read MPIDR_EL1 into Xt
Register access is encoded as follows:
The EDDEVAFF0 and EDDEVAFF1 can be accessed through the internal memory-mapped
interface and the external debug interface, offsets
0xFA8
and
0xFAC
respectively.
4.3.3 Revision ID Register
The REVIDR_EL1 characteristics are:
Purpose Provides implementation-specific minor revision information that can be
interpreted only in conjunction with the Main ID Register.
Table 4-15 MPIDR_EL1 bit assignments
Bits Name Function
[63:40] - Reserved,
RES0.
[39:32] Aff3 Affinity level 3. Highest level affinity field.
Reserved,
RES0.
[31] - Reserved,
RES1.
[30] U Indicates a single core system, as distinct from core 0 in a cluster. This value is:
0
Core is part of a cluster.
[29:25] - Reserved,
RES0.
[24] MT Indicates whether the lowest level of affinity consists of logical cores that are implemented using a
multi-threading type approach. This value is:
0
Performance of cores at the lowest affinity level is largely independent.
[23:16] Aff2 Affinity level 2. Second highest level affinity field.
Indicates the value read in the CLUSTERIDAFF2 configuration signal.
[15:8] Aff1 Affinity level 1. Third highest level affinity field.
Indicates the value read in the CLUSTERIDAFF1 configuration signal.
[7:0] Aff0 Affinity level 0. Lowest level affinity field.
Indicates the core number in the Cortex-A53 processor. The possible values are:
0x0
A cluster with one core only.
0x0
,
0x1
A cluster with two cores.
0x0
,
0x1
,
0x2
A cluster with three cores.
0x0
,
0x1
,
0x2
,
0x3
A cluster with four cores.
Table 4-16 MPIDR access encoding
op0 op1 CRn CRm op2
11 000 0000 0000 101
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