ARM Cortex-A53 MPCore - Page 78

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-17
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
Configurations REVIDR_EL1 is architecturally mapped to AArch32 register REVIDR.
See Revision ID Register on page 4-159.
Attributes REVIDR_EL1 is a 32-bit register.
Figure 4-3 shows the REVIDR_EL1 bit assignments.
Figure 4-3 REVIDR_EL1 bit assignments
Table 4-17 shows the REVIDR_EL1 bit assignments.
To access the REVIDR_EL1:
MRS <Xt>, REVIDR_EL1 ; Read REVIDR_EL1 into Xt
Register access is encoded as follows:
4.3.4 AArch32 Processor Feature Register 0
The ID_PFR0_EL1 characteristics are:
Purpose Gives top-level information about the instruction sets supported by the
processor in AArch32.
Usage constraints This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RORORORO RO
31 0
ID number
Table 4-17 REVIDR_EL1 bit assignments
Bits Name Function
[31:0] ID number Implementation-specific revision information. The reset value is determined by the specific Cortex-A53
MPCore implementation.
0x00000000 Revision code is zero.
Table 4-18 REVIDR_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0000 110
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RORORORO RO