System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-19
ID021414 Non-Confidential
Configurations ID_PFR1_EL1 is architecturally mapped to AArch32 register ID_PFR1.
See Processor Feature Register 1 on page 4-162.
Attributes ID_PFR1_EL1 is a 32-bit register.
Figure 4-5 shows the ID_PFR1_EL1 bit assignments.
Figure 4-5 ID_PFR1_EL1 bit assignments
Table 4-21 shows the ID_PFR1_EL1 bit assignments.
To access the ID_PFR1_EL1:
MRS <Xt>, ID_PFR1_EL1 ; Read ID_PFR1_EL1 into Xt
Register access is encoded as follows:
4.3.6 AArch32 Debug Feature Register 0
The ID_DFR0_EL1 characteristics are:
Purpose Provides top level information about the debug system in AArch32.
Table 4-21 ID_PFR1_EL1 bit assignments
Bits Name Function
[31:28] GIC CPU GIC CPU support:
0x0
GIC CPU interface is disabled, GICCDISABLE is HIGH.
0x1
GIC CPU interface is enabled.
[27:20] - Reserved,
RES0.
[19:16] GenTimer Generic Timer support:
0x1
Generic Timer supported.
[15:12] Virtualization Virtualization support:
0x1
Virtualization implemented.
[11:8] MProgMod M profile programmers' model support:
0x0
Not supported.
[7:4] Security Security support:
0x1
Security implemented. This includes support for Monitor mode and the SMC instruction.
[3:0] ProgMod Indicates support for the standard programmers model for ARMv4 and later.
Model must support User, FIQ, IRQ, Supervisor, Abort, Undefined, and System modes:
0x1
Supported.
Table 4-22 REVIDR access encoding
op0 op1 CRn CRm op2
1111 000 0000 0001 001
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