ARM Cortex-A53 MPCore - Page 81

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-20
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
Configurations ID_DFR0_EL1 is architecturally mapped to AArch32 register ID_DFR0.
See Debug Feature Register 0 on page 4-163.
Attributes ID_DFR0_EL1 is a 32-bit register.
Figure 4-6 shows the ID_DFR0_EL1 bit assignments.
Figure 4-6 ID_DFR0_EL1 bit assignments
Table 4-23 shows the ID_DFR0_EL1 bit assignments.
To access the ID_DFR0_EL1:
MRS <Xt>, ID_DFR0_EL1 ; Read ID_DFR0_EL1 into Xt
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RORORORO RO
31 12 11 8 7 0
RES0
4324 23 20 19 16 1528 27
PerfMon MProfDbg MMapTrc CopTrc CopSDbg CopDbgReserved
Table 4-23 ID_DFR0_EL1 bit assignments
Bits Name Function
[31:28] - Reserved,
RES0.
[27:24] PerfMon Indicates support for performance monitor model:
0x3 Support for Performance Monitor Unit version 3 (PMUv3) system registers.
[23:20] MProfDbg Indicates support for memory-mapped debug model for M profile processors:
0x0 Processor does not support M profile Debug architecture.
[19:16] MMapTrc Indicates support for memory-mapped trace model:
0x1 Support for ARM trace architecture, with memory-mapped access.
In the Trace registers, the ETMIDR gives more information about the implementation.
[15:12] CopTrc Indicates support for coprocessor-based trace model:
0x0 Processor does not support ARM trace architecture with CP14 access.
[11:8] - Reserved,
RES0.
[7:4] CopSDbg Indicates support for coprocessor-based Secure debug model:
0x6 Processor supports v8 Debug architecture, with CP14 access.
[3:0] CopDbg Indicates support for coprocessor-based debug model:
0x6 Processor supports v8 Debug architecture, with CP14 access.