System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-26
ID021414 Non-Confidential
4.3.11 AArch32 Memory Model Feature Register 3
The ID_MMFR3_EL1 characteristics are:
Purpose Provides information about the memory model and memory management
support in AArch32.
Usage constraints This register is accessible as follows:
Configurations ID_MMFR3_EL1 is architecturally mapped to AArch32 register
ID_MMFR3. See Memory Model Feature Register 3 on page 4-170.
Attributes ID_MMFR3_EL1 is a 32-bit register.
Figure 4-10 shows the ID_MMFR3_EL1 bit assignments.
Figure 4-10 ID_MMFR3_EL1 bit assignments
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RORORORO RO
31 12 11 8 7 04328 27 24 23 20 19 16 15
ReservedCohWalkCMemSzSupersec MaintBcst BPMaint CMaintSW CMaintVA
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