System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-25
ID021414 Non-Confidential
Table 4-29 shows the ID_MMFR2_EL1 bit assignments.
To access the ID_MMFR2_EL1:
MRS <Xt>, ID_MMFR2_EL1 ; Read ID_MMFR2_EL1 into Xt
Register access is encoded as follows:
Table 4-29 ID_MMFR2_EL1 bit assignments
Bits Name Function
[31:28] HWAccFlg Hardware access flag. Indicates support for a hardware access flag, as part of the VMSAv7 implementation:
0x0
Not supported.
[27:24] WFIStall Wait For Interrupt Stall. Indicates the support for Wait For Interrupt (WFI) stalling:
0x1
Support for WFI stalling.
[23:20] MemBarr Memory Barrier. Indicates the supported CP15 memory barrier operations.
0x2
Supported CP15 memory barrier operations are:
• Data Synchronization Barrier (DSB).
• Instruction Synchronization Barrier (ISB).
• Data Memory Barrier (DMB).
[19:16] UniTLB Unified TLB. Indicates the supported TLB maintenance operations, for a unified TLB implementation.
0x6
Supported unified TLB maintenance operations are:
• Invalidate all entries in the TLB.
• Invalidate TLB entry by MVA.
• Invalidate TLB entries by ASID match.
• Invalidate instruction TLB and data TLB entries by MVA All ASID. This is a shared
unified TLB operation.
• Invalidate Hyp mode unified TLB entry by MVA.
• Invalidate entire Non-secure EL1 and EL0 unified TLB.
• Invalidate entire Hyp mode unified TLB.
•
TLBIMVALIS
,
TLBIMVAALIS
,
TLBIMVALHIS
,
TLBIMVAL
,
TLBIMVAAL
, and
TLBIMVALH
.
•
TLBIIPAS2IS
,
TLBIIPAS2LIS
,
TLBIIPAS2
, and
TLBIIPAS2L
.
[15:12] HvdTLB Harvard TLB. Indicates the supported TLB maintenance operations, for a Harvard TLB implementation:
0x0
Not supported.
[11:8] LL1HvdRng L1 Harvard cache Range. Indicates the supported L1 cache maintenance range operations, for a Harvard
cache implementation:
0x0
Not supported.
[7:4] L1HvdBG L1 Harvard cache Background fetch. Indicates the supported L1 cache background prefetch operations, for
a Harvard cache implementation:
0x0
Not supported.
[3:0] L1HvdFG L1 Harvard cache Foreground fetch. Indicates the supported L1 cache foreground prefetch operations, for
a Harvard cache implementation:
0x0
Not supported.
Table 4-30 ID_MMFR2_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0001 110
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