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ARM Cortex-A53 MPCore
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System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-24
ID021414 Non-Confidential
4.3.10 AArch32 Memory Model Feature Register 2
The ID_MMFR2_EL1 characteristics are:
Purpose Provides information about the implemented memory model and memory
management support in AArch32.
Usage constraints This register is accessible as follows:
Configurations ID_MMFR2_EL1 is architecturally mapped to AArch32 register
ID_MMFR2. See Memory Model Feature Register 2 on page 4-168.
Attributes ID_MMFR2_EL1 is a 32-bit register.
Figure 4-9 shows the ID_MMFR2_EL1 bit assignments.
Figure 4-9 ID_MMFR2_EL1 bit assignments
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RORORORO RO
31 12 11 8 7 0
HWAccFlg
4328 27 24 23 20 19 16 15
WFIStall MemBarr UniTLB HvdTLB LL1HvdRng L1HvdBG L1HvdFG

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