System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-23
ID021414 Non-Confidential
Configurations ID_MMFR1_EL1 is architecturally mapped to AArch32 register
ID_MMFR1. See Memory Model Feature Register 1 on page 4-166.
Attributes ID_MMFR1_EL1 is a 32-bit register.
Figure 4-8 shows the ID_MMFR1_EL1 bit assignments.
Figure 4-8 ID_MMFR1_EL1 bit assignments
Table 4-27 shows the ID_MMFR1_EL1 bit assignments.
To access the ID_MMFR1_EL1:
MRS <Xt>, ID_MMFR1_EL1 ; Read ID_MMFR1_EL1 into Xt
Register access is encoded as follows:
Table 4-27 ID_MMFR1_EL1 bit assignments
Bits Name Function
[31:28] BPred Indicates branch predictor management requirements:
0x4
For execution correctness, branch predictor requires no flushing at any time.
[27:24] L1TstCln Indicates the supported L1 Data cache test and clean operations, for Harvard or unified cache implementation:
0x0
None supported.
[23:20] L1Uni Indicates the supported entire L1 cache maintenance operations, for a unified cache implementation:
0x0
None supported.
[19:16] L1Hvd Indicates the supported entire L1 cache maintenance operations, for a Harvard cache implementation:
0x0
None supported.
[15:12] L1UniSW Indicates the supported L1 cache line maintenance operations by set/way, for a unified cache implementation:
0x0
None supported.
[11:8] L1HvdSW Indicates the supported L1 cache line maintenance operations by set/way, for a Harvard cache
implementation:
0x0
None supported.
[7:4] L1UniVA Indicates the supported L1 cache line maintenance operations by MVA, for a unified cache implementation:
0x0
None supported.
[3:0] L1HvdVA Indicates the supported L1 cache line maintenance operations by MVA, for a Harvard cache implementation:
0x0
None supported.
Table 4-28 ID_MMFR1_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0001 101
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