System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-22
ID021414 Non-Confidential
Table 4-25 shows the ID_MMFR0_EL1 bit assignments.
To access the ID_MMFR0_EL1:
MRS <Xt>, ID_MMFR0_EL1 ; Read ID_MMFR0_EL1 into Xt
Register access is encoded as follows:
4.3.9 AArch32 Memory Model Feature Register 1
The ID_MMFR1_EL1 characteristics are:
Purpose Provides information about the memory model and memory management
support in AArch32.
Usage constraints This register is accessible as follows:
Table 4-25 ID_MMFR0_EL1 bit assignments
Bits Name Function
[31:28] InnerShr Indicates the innermost shareability domain implemented:
0x1
Implemented with hardware coherency support.
[27:24] FCSE Indicates support for Fast Context Switch Extension (FCSE):
0x0
Not supported.
[23:20] AuxReg Indicates support for Auxiliary registers:
0x1
Support for Auxiliary Control Register only.
[19:16] TCM Indicates support for TCMs and associated DMAs:
0x0
Not supported.
[15:12] ShareLvl Indicates the number of shareability levels implemented:
0x1
Two levels of shareability implemented.
[11:8] OuterShr Indicates the outermost shareability domain implemented:
0x1
Implemented with hardware coherency support.
[7:4] PMSA Indicates support for a Protected Memory System Architecture (PMSA):
0x0
Not supported.
[3:0] VMSA Indicates support for a Virtual Memory System Architecture (VMSA).
0x5
Support for:
• VMSAv7, with support for remapping and the Access flag.
• The PXN bit in the Short-descriptor translation table format descriptors.
• The Long-descriptor translation table format.
Table 4-26 ID_MMFR0_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0001 100
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RORORORO RO
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