ARM Cortex-A53 MPCore - Page 98

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-37
ID021414 Non-Confidential
Table 4-43 shows the ID_ISAR5_EL1 bit assignments.
To access the ID_ISAR5_EL1:
MRS <Xt>, ID_ISAR5_EL1 ; Read ID_ISAR5_EL1 into Xt
Register access is encoded as follows:
4.3.18 AArch64 Processor Feature Register 0
The ID_AA64PFR0_EL1 characteristics are:
Purpose Provides additional information about implemented processor features in
AArch64.
Note
The optional Advanced SIMD and Floating-point extension is not
included in the base product of the processor. ARM requires licensees to
have contractual rights to obtain the Advanced SIMD and Floating-point
extension.
Usage constraints This register is accessible as follows:
Table 4-43 ID_ISAR5_EL1 bit assignments
Bits Name Function
[31:20] - Reserved,
RES0.
[19:16] CRC32 Indicates whether CRC32 instructions are implemented in AArch32 state:
0x1 CRC32 instructions are implemented.
[15:12] SHA2 Indicates whether SHA2 instructions are implemented in AArch32 state:
0x0 Cryptography Extensions are not implemented or are disabled.
0x1 SHA256H , SHA256H2 , SHA256SU0 , and SHA256SU1 instructions are implemented.
[11:8] SHA1 Indicates whether SHA1 instructions are implemented in AArch32 state:
0x0 Cryptography Extensions are not implemented or are disabled.
0x1 SHA1C , SHA1P , SHA1M , SHA1H , SHA1SU0 , and SHA1SU1 instructions are implemented.
[7:4] AES Indicates whether AES instructions are implemented in AArch32 state:
0x0 Cryptography Extensions are not implemented or are disabled.
0x2 AESE , AESD , AESMC and AESIMC , plus PMULL and PMULL2 instructions operating on 64-bit
data.
[3:0] SEVL Indicates whether the
SEVL instruction is implemented:
0x1 SEVL implemented to send event local.
Table 4-44 ID_ISAR5_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0010 101
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RORORORO RO