System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-36
ID021414 Non-Confidential
MRS <Xt>, ID_ISAR4_EL1 ; Read ID_ISAR4_EL1 into Xt
Register access is encoded as follows:
4.3.17 AArch32 Instruction Set Attribute Register 5
The ID_ISAR5_EL1 characteristics are:
Purpose Provides information about the instruction sets that the processor
implements.
The optional Advanced SIMD and Floating-point extension is not
included in the base product of the processor. ARM requires licensees to
have contractual rights to obtain the Advanced SIMD and Floating-point
extension.
Usage constraints This register is accessible as follows:
Configurations ID_ISAR5_EL1 is architecturally mapped to AArch32 register
ID_ISAR5. See Instruction Set Attribute Register 5 on page 4-181.
Attributes ID_ISAR5_EL1 is a 32-bit register.
Figure 4-16 shows the ID_ISAR5_EL1 bit assignments.
Figure 4-16 ID_ISAR5_EL1 bit assignments
Table 4-42 ID_ISAR4_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0010 100
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RORORORO RO
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