ARM Cortex-A53 MPCore - Page 96

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-35
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
Configurations ID_ISAR4_EL1 is architecturally mapped to AArch32 register
ID_ISAR4. See Instruction Set Attribute Register 4 on page 4-179.
Attributes ID_ISAR4_EL1 is a 32-bit register.
Figure 4-15 shows the ID_ISAR4_EL1 bit assignments.
Figure 4-15 ID_ISAR4_EL1 bit assignments
Table 4-41 shows the ID_ISAR4_EL1 bit assignments.
To access the ID_ISAR4_EL1:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RORORORO RO
31 24 23 20 19 16 15 12 11 8 7 4 3 0
SynchPrim_frac
SWP_frac
28 27
PSR_M Barrier SMC Writeback WithShifts Unpriv
Table 4-41 ID_ISAR4_EL1 bit assignments
Bits Name Function
[31:28] SWP_frac Indicates support for the memory system locking the bus for
SWP or SWPB instructions:
0x0 SWP and SWPB instructions not implemented.
[27:24] PSR_M Indicates the implemented M profile instructions to modify the PSRs:
0x0 None implemented.
[23:20] SynchPrim_frac This field is used with the ID_ISAR3.SynchPrim field to indicate the implemented Synchronization
Primitive instructions:
0x0 • The LDREX and STREX instructions.
• The
CLREX , LDREXB , LDREXH , STREXB , and STREXH instructions.
• The LDREXD and STREXD instructions.
[19:16] Barrier Indicates the supported Barrier instructions in the A32 and T32 instruction sets:
0x1 The DMB , DSB , and ISB barrier instructions.
[15:12] SMC Indicates the implemented
SMC instructions:
0x1 The SMC instruction.
[11:8] WriteBack Indicates the support for Write-Back addressing modes:
0x1 Processor supports all of the Write-Back addressing modes defined in ARMv8.
[7:4] WithShifts Indicates the support for instructions with shifts.
0x4 • Support for shifts of loads and stores over the range LSL 0-3.
• Support for other constant shift options, both on load/store and other instructions.
• Support for register-controlled shift options.
[3:0] Unpriv Indicates the implemented unprivileged instructions.
0x2 • The LDRBT , LDRT , STRBT , and STRT instructions.
• The LDRHT , LDRSBT , LDRSHT , and STRHT instructions.