ARM Cortex-A53 MPCore - Page 95

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-34
ID021414 Non-Confidential
Table 4-39 shows the ID_ISAR3_EL1 bit assignments.
To access the ID_ISAR3_EL1:
MRS <Xt>, ID_ISAR3_EL1 ; Read ID_ISAR3_EL1 into Xt
Register access is encoded as follows:
4.3.16 AArch32 Instruction Set Attribute Register 4
The ID_ISAR4_EL1 characteristics are:
Purpose Provides information about the instruction sets implemented by the
processor in AArch32.
Table 4-39 ID_ISAR3_EL1 bit assignments
Bits Name Function
[31:28] ThumbEE Indicates the implemented Thumb Execution Environment (T32EE) instructions:
0x0 None implemented.
[27:24] TrueNOP Indicates support for True NOP instructions:
0x1 True NOP instructions in both the A32 and T32 instruction sets, and additional
NOP-compatible hints.
[23:20] ThumbCopy Indicates the support for T32 non flag-setting
MOV instructions:
0x1 Support for T32 instruction set encoding T1 of the MOV (register) instruction, copying from
a low register to a low register.
[19:16] TabBranch Indicates the implemented Table Branch instructions in the T32 instruction set.
0x1 The TBB and TBH instructions.
[15:12] SynchPrim Indicates the implemented Synchronization Primitive instructions:
0x2 • The LDREX and STREX instructions.
• The
CLREX , LDREXB , STREXB , and STREXH instructions.
• The
LDREXD and STREXD instructions.
[11:8] SVC Indicates the implemented SVC instructions:
0x1 The SVC instruction.
[7:4] SIMD Indicates the implemented Single Instruction Multiple Data (SIMD) instructions.
0x3 • The SSAT and USAT instructions, and the Q bit in the PSRs.
• The PKHBT , PKHTB , QADD16 , QADD8 , QASX , QSUB16 , QSUB8 , QSAX , SADD16 , SADD8 , SASX , SEL ,
SHADD16 , SHADD8 , SHASX , SHSUB16 , SHSUB8 , SHSAX , SSAT16 , SSUB16 , SSUB8 , SSAX , SXTAB16 ,
SXTB16 , UADD16 , UADD8 , UASX , UHADD16 , UHADD8 , UHASX , UHSUB16 , UHSUB8 , UHSAX , UQADD16 ,
UQADD8 , UQASX , UQSUB16 , UQSUB8 , UQSAX , USAD8 , USADA8 , USAT16 , USUB16 , USUB8 , USAX ,
UXTAB16 , UXTB16 instructions, and the GE[3:0] bits in the PSRs.
[3:0] Saturate Indicates the implemented Saturate instructions:
0x1 The QADD , QDADD , QDSUB , QSUB and the Q bit in the PSRs.
Table 4-40 ID_ISAR3_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0010 011