System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-33
ID021414 Non-Confidential
4.3.15 AArch32 Instruction Set Attribute Register 3
The ID_ISAR3_EL1 characteristics are:
Purpose Provides information about the instruction sets implemented by the
processor in AArch32.
Usage constraints This register is accessible as follows:
Configurations ID_ISAR3_EL1 is architecturally mapped to AArch32 register
ID_ISAR3. See Instruction Set Attribute Register 3 on page 4-178.
Attributes ID_ISAR3_EL1 is a 32-bit register.
Figure 4-14 shows the ID_ISAR3_EL1 bit assignments.
Figure 4-14 ID_ISAR3_EL1 bit assignments
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RORORORO RO
To Next Page
Loading...
