ARM Cortex-A53 MPCore - Page 93

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-32
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Table 4-37 shows the ID_ISAR2_EL1 bit assignments.
To access the ID_ISAR2_EL1:
MRS <Xt>, ID_ISAR2_EL1 ; Read ID_ISAR2_EL1 into Xt
Register access is encoded as follows:
Table 4-37 ID_ISAR2_EL1 bit assignments
Bits Name Function
[31:28] Reversal Indicates the implemented Reversal instructions:
0x2 The REV , REV16 , REVSH , and RBIT instructions.
[27:24] PSR_AR Indicates the implemented A and R profile instructions to manipulate the PSR:
0x1 The MRS and MSR instructions, and the exception return forms of data-processing
instructions.
Note
The exception return forms of the data-processing instructions are:
• In the A32 instruction set, data-processing instructions with the PC as the destination and the S bit
set.
• In the T32 instruction set, the
SUBS PC , LR , #N instruction.
[23:20] MultU Indicates the implemented advanced unsigned Multiply instructions:
0x2 The UMULL , UMLAL and UMAAL instructions.
[19:16] MultS Indicates the implemented advanced signed Multiply instructions.
0x3 • The SMULL and SMLAL instructions.
• The
SMLABB , SMLABT , SMLALBB , SMLALBT , SMLALTB , SMLALTT , SMLATB , SMLATT , SMLAWB ,
SMLAWT , SMULBB , SMULBT , SMULTB , SMULTT , SMULWB , SMULWT instructions, and the Q bit in
the PSRs.
• The
SMLAD , SMLADX , SMLALD , SMLALDX , SMLSD , SMLSDX , SMLSLD , SMLSLDX , SMMLA , SMMLAR ,
SMMLS , SMMLSR , SMMUL , SMMULR , SMUAD , SMUADX , SMUSD , and SMUSDX instructions.
[15:12] Mult Indicates the implemented additional Multiply instructions:
0x2 The MUL , MLA and MLS instructions.
[11:8] MultiAccessInt Indicates the support for interruptible multi-access instructions:
0x0 No support. This means the LDM and STM instructions are not interruptible.
[7:4] MemHint Indicates the implemented memory hint instructions:
0x4 The PLD instruction.
The
PLI instruction.
The PLDW instruction.
[3:0] LoadStore Indicates the implemented additional load/store instructions:
0x2 The LDRD and STRD instructions.
The Load Acquire (
LDAB , LDAH , LDA , LDAEXB , LDAEXH , LDAEX , and LDAEXD ) and Store Release
(
STLB , STLH , STL , STLEXB , STLEXH , STLEX , and STLEXD ) instructions.
Table 4-38 ID_ISAR2_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0010 010