ARM Cortex-A53 MPCore - Page 92

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-31
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
Configurations ID_ISAR2_EL1 is architecturally mapped to AArch32 register
ID_ISAR2. See Instruction Set Attribute Register 2 on page 4-175.
Attributes ID_ISAR2_EL1 is a 32-bit register.
Figure 4-13 shows the ID_ISAR2_EL1 bit assignments.
Figure 4-13 ID_ISAR2_EL1 bit assignments
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RORORORO RO
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
MultiAccessInt
Reversal PSR_AR MultU MultS Mult MemHint LoadStore