ARM Cortex-A53 MPCore - Page 91

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-30
ID021414 Non-Confidential
Table 4-35 shows the ID_ISAR1_EL1 bit assignments.
To access the ID_ISAR1_EL1:
MRS <Xt>, ID_ISAR1_EL1 ; Read ID_ISAR1_EL1 into Xt
Register access is encoded as follows:
4.3.14 AArch32 Instruction Set Attribute Register 2
The ID_ISAR2_EL1 characteristics are:
Purpose Provides information about the instruction sets implemented by the
processor in AArch32.
Table 4-35 ID_ISAR1_EL1 bit assignments
Bits Name Function
[31:28] Jazelle Indicates the implemented Jazelle state instructions:
0x1 Adds the BXJ instruction, and the J bit in the PSR. This setting might indicate a trivial
implementation of the Jazelle extension.
[27:24] Interwork Indicates the implemented Interworking instructions:
0x3 • The BX instruction, and the T bit in the PSR.
• The
BLX instruction. The PC loads have BX -like behavior.
• Data-processing instructions in the A32 instruction set with the PC as the destination
and the S bit clear, have
BX -like behavior.
[23:20] Immediate Indicates the implemented data-processing instructions with long immediates:
0x1 • The MOVT instruction.
• The
MOV instruction encodings with zero-extended 16-bit immediates.
• The T32 ADD and SUB instruction encodings with zero-extended 12-bit immediates, and
other
ADD , ADR , and SUB encodings cross-referenced by the pseudocode for those
encodings.
[19:16] IfThen Indicates the implemented
If-Then instructions in the T32 instruction set:
0x1 The IT instructions, and the IT bits in the PSRs.
[15:12] Extend Indicates the implemented Extend instructions:
0x2 • The SXTB , SXTH , UXTB , and UXTH instructions.
• The
SXTB16 , SXTAB , SXTAB16 , SXTAH , UXTB16 , UXTAB , UXTAB16 , and UXTAH instructions.
[11:8] Except_AR Indicates the implemented A profile exception-handling instructions:
0x1 The SRS and RFE instructions, and the A profile forms of the CPS instruction.
[7:4] Except Indicates the implemented exception-handling instructions in the A32 instruction set:
0x1 The LDM (exception return), LDM (user registers), and STM (user registers) instruction versions.
[3:0] Endian Indicates the implemented Endian instructions:
0x1 The SETEND instruction, and the E bit in the PSRs.
Table 4-36 ID_ISAR1_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0010 001