System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-29
ID021414 Non-Confidential
MRS <Xt>, ID_ISAR0_EL1 ; Read ID_ISAR0_EL1 into Xt
Register access is encoded as follows:
4.3.13 AArch32 Instruction Set Attribute Register 1
The ID_ISAR1_EL1 characteristics are:
Purpose Provides information about the instruction sets implemented by the
processor in AArch32.
Usage constraints This register is accessible as follows:
Configurations ID_ISAR1_EL1 is architecturally mapped to AArch32 register
ID_ISAR1. See Instruction Set Attribute Register 1 on page 4-173.
Attributes ID_ISAR1_EL1 is a 32-bit register.
Figure 4-12 shows the ID_ISAR1_EL1 bit assignments.
Figure 4-12 ID_ISAR1_EL1 bit assignments
Table 4-34 ID_ISAR0_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0010 000
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RORORORO RO
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
Jazelle Interwork Immediate IfThen Extend Except_AR Except Endian
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