ARM Cortex A9 User Manual

Preload Engine
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 9-2
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9.1 About the Preload Engine
If implemented, the PLE loads selected regions of memory into the L2 interface. Use the MCRR
preload channel operation to program the PLE. Dedicated events monitor the behavior of the
memory region. Additional L2C-310 events can also monitor PLE behavior.
The preload operation parameters enter the PLE FIFO that includes:
• programmed parameters:
— base address
— length of stride
— number of blocks.
• a valid bit
• an NS state bit
•a Translation Table Base (TTB) address
•an Address Space Identifier (ASID) value.
Preload blocks can span multiple page entries. Programmed entries can still be valid in case of
context switches.
The Preload Engine handles cache line preload requests in the same way as a standard PLD
request except that it uses its own TTB and ASID parameters. If there is a translation abort, the
preload request is ignored and the Preload Engine issues the next request.
Not all the MMU settings are saved. The Domain, Tex-Remap, Primary Remap, Normal
Remap, and Access Permission registers are not saved. As a consequence, a write operation in
any of these registers causes a flush of the entire FIFO and of the active channel. Additionally,
for TLB maintenance operations, the maintenance operation must also be applied to the FIFO
entries. This is done as follows:
On Invalidate by MVA and ASID
Invalidate all entries with a matching ASID.
On Invalidate by ASID
Invalidate all entries with a matching ASID.
On Invalidate by MVA all ASID
Flush the entire FIFO.
On Invalidate entire TLB
Flush the entire FIFO.
.
These rules are also applicable to the PLE active channel.
The Preload Engine defines the following
MCRR instruction to use with the preload blocks.
MCRR p15, 0, <Rt>,<Rt2> c11; Program new PLE channel
The number of entries in the FIFO can be set as an RTL configuration design choice. Available
sizes are:
• 16 entries
•8 entries
•4 entries.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design