ARM Cortex A9 User Manual

Preface
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. vii
ID073015 Non-Confidential
About this book
This book is for the Cortex-A9 processor.
Product revision status
The rnpn identifier indicates the revision status of the product described in this book, where:
rn Identifies the major revision of the product.
pn Identifies the minor revision or modification status of the product.
Intended audience
This book is written for hardware and software engineers implementing Cortex-A9 system
designs. It provides information that enables designers to integrate the processor into a target
system.
Note
• The Cortex-A9 processor is a single core processor.
• The multiprocessor variant, the Cortex-A9 MPCore
™
processor, consists of between one
and four Cortex-A9 processors and a Snoop Control Unit (SCU). See the Cortex-A9
MPCore Technical Reference Manual for a description.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
Read this for an introduction to the Cortex-A9 processor and its features.
Chapter 2 Functional Description
Read this for a description of the functionality of the Cortex-A9 processor.
Chapter 3 Programmers Model
Read this for a description of the Cortex-A9 registers and programming
information.
Chapter 4 System Control
Read this for a description of the Cortex-A9 system control registers, their
structure, operation, and how to use them.
Chapter 5 Jazelle DBX registers
Read this for a description of the CP14 coprocessor and its non-debug use for
Jazelle DBX.
Chapter 6 Memory Management Unit
Read this for a description of the Cortex-A9 Memory Management Unit (MMU).
Chapter 7 Level 1 Memory System
Read this for a description of the Cortex-A9 level one memory system, including
caches, Translation Lookaside Buffers (TLB), and store buffer.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design