Cycle Timings and Interlock Behavior
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. B-4
ID073015 Non-Confidential
B.3 Load and store instructions
Load and store instructions are classed as:
• single load and store instructions such as
LDR
instructions
• load and store multiple instructions such as
LDM
instructions.
For load multiple and store multiple instructions, the number of registers in the register list
usually determines the number of cycles required to execute a load or store instruction.
The Cortex-A9 processor has an optimized path from a load instruction to a subsequent data
processing instruction, saving 1 cycle on the load-use penalty.
This path is used when the following conditions are met:
• the data-processing instruction is an arithmetical, a logical or a saturation operation
• the data-processing instruction does not require any shift
• the load instruction does not require sign extension
• the load instruction is not conditional.
Table B-2 shows cycle timing for single load and store operations. The result latency is the
latency of the first loaded register.
Table B-2 Single load and store operation cycle timings
Instruction cycles AGU cycles
Result latency
Fast forward cases other cases
LDR ,[reg]
LDR ,[reg imm]
LDR ,[reg reg]
LDR ,[reg reg LSL #2]
12 3
LDR ,[reg reg LSL reg]
LDR ,[reg reg LSR reg]
LDR ,[reg reg ASR reg]
LDR ,[reg reg ROR reg]
LDR
,[
reg
reg
,
RRX
]
13 4
LDRB
,[reg]
LDRB
,[reg imm]
LDRB
,[reg reg]
LDRB
,[reg reg LSL #2]
LDRH
,[reg]
LDRH
,[reg imm]
LDRH
,[reg reg]
LDRH
,[reg reg LSL #2]
23 4
LDRB ,[reg reg LSL reg]
LDRB ,[reg reg ASR reg]
LDRB ,[reg reg LSL reg]
LDRB ,[reg reg ASR reg]
LDRH ,[reg reg LSL reg]
LDRH ,[reg reg ASR reg]
LDRH ,[reg reg LSL reg]
LDRH ,[reg reg ASR reg]
24 5
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