ARM Cortex A9 - Exception Flags Signal

Signal Descriptions
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-17
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A.9 Exception flags signal
Table A-19 shows the DEFLAGS signal.
For additional information on the FPSCR, see the Cortex-A9 Floating-Point Unit (FPU)
Technical Reference Manual and the Cortex-A9 NEON Media Processing Engine Technical
Reference Manual.
Table A-19 DEFLAGS signal
Name I/O Destination Description
DEFLAGS[6:0] O Exception monitoring unit Data engine output flags. Only implemented if the Cortex-A9 processor
includes a Data engine, either an MPE or FPU.
If the DE is MPE:
• Bit [6] gives the value of FPSCR[27]
• Bit [5] gives the value of FPSCR[7]
• Bits [4:0] give the value of FPSCR[4:0].
If the DE is FPU:
• Bit [6] is zero.
• Bit [5] gives the value of FPSCR[7]
• Bits [4:0] give the value of FPSCR[4:0].