ARM Cortex A9 User Manual

Signal Descriptions
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-17
ID073015 Non-Confidential
A.9 Exception flags signal
Table A-19 shows the DEFLAGS signal.
For additional information on the FPSCR, see the Cortex-A9 Floating-Point Unit (FPU)
Technical Reference Manual and the Cortex-A9 NEON Media Processing Engine Technical
Reference Manual.
Table A-19 DEFLAGS signal
Name I/O Destination Description
DEFLAGS[6:0] O Exception monitoring unit Data engine output flags. Only implemented if the Cortex-A9 processor
includes a Data engine, either an MPE or FPU.
If the DE is MPE:
• Bit [6] gives the value of FPSCR[27]
• Bit [5] gives the value of FPSCR[7]
• Bits [4:0] give the value of FPSCR[4:0].
If the DE is FPU:
• Bit [6] is zero.
• Bit [5] gives the value of FPSCR[7]
• Bits [4:0] give the value of FPSCR[4:0].

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design